1. Field of the Invention
The present invention relates to an electrically data-rewritable nonvolatile semiconductor memory device.
2. Description of the Related Art
Conventionally, an LSI is formed by integrating elements in a two-dimensional plane on a silicon substrate. The only way to increase storage capacity of memory is by reducing dimensions of (miniaturizing) elements. However, in recent years, even this miniaturization is becoming difficult in terms of cost and technology. Improvements in photolithographic technology are necessary for miniaturization, but, for example, in current ArF immersion lithography technology, a rule of around 40 nm represents the resolution limit, and further miniaturization requires introduction of EUV steppers. However, EUV steppers are expensive and unrealistic when considering costs. Moreover, even if miniaturization is achieved, it is expected that physical limitations such as those of withstand voltage between elements are encountered, unless the drive voltage and so on are scaled. In other words, there is a high possibility that operation as a device becomes difficult.
Accordingly, in recent years, many semiconductor memory devices are proposed in which memory cells are disposed three-dimensionally in order to increase a degree of integration of memory (refer to Japanese Unexamined Patent Application Publication No. 2007-266143).
One conventional semiconductor memory device in which memory cells are disposed three-dimensionally uses transistors with a cylindrical column type structure (Japanese Unexamined Patent Application Publication No. 2007-266143). The semiconductor memory device using the transistors with the cylindrical column type structure is provided with multi-layer stacked conductive layers configured to form gate electrodes, and pillar-shaped columnar semiconductor layers. The columnar semiconductor layer functions as a channel (body) portion of the transistors. A vicinity of the columnar semiconductor layer is provided with a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) layer. A configuration including these stacked conductive layer, columnar semiconductor layer, and MONOS layer is called a memory string.
A plurality of the above-described memory strings are connected to a common bit line via select transistors. Accordingly, the greater becomes the number of memory strings connected to one bit line, the larger becomes the sum total of current flowing in unselected memory strings. As a result, it becomes difficult to perform a read accurately.